Design Engineer II
il y a 2 semaines
Cadence is looking for an Employee-Student PhD for 3 years to work on
Architectural Analysis of Chiplet Based Systems for Automotive ApplicationsBackground
Chiplet-based system design is emerging as a transformative approach in semiconductor technology, enabling a more modular and efficient way to build complex systems-on-chip (SoCs). Notably, Cadence has made significant strides in this area by unveiling the first system chiplet that includes a system processor, a safety management processor, memory controllers, NoC and UCIe. Chiplets in a system can be individually optimized enhancing overall system performance, reducing power consumption, and lowering design costs through reuse and interoperability. As industries increasingly shift toward this paradigm, there is a growing need for comprehensive system-level analysis of chiplet-based architectures to ensure functionality and efficiency in real-world applications both at the chiplet and at the full-system level. With Cadence as a pivotal partner in IMEC’s Automotive Chiplet Program, this research will particularly focus on the program’s key goal - evaluating chiplet architectures for automotive SoCs, that combines performance, energy efficiency, robustness, and cost.
Despite the advantages of chiplet-based systems, evaluating chiplets at a system level remains a challenging task. Current methodologies may not adequately capture the intricacies of chiplet interactions and their impact on overall system performance. This provides a unique opportunity for research focused on developing robust analysis frameworks that can effectively evaluate chiplet-based designs in diverse conditions and architectures that meet the demands of automotive applications. The successful candidate will explore these challenges, develop methodologies for architectural exploration, and identify KPIs to drive innovative solutions for chiplet-based automotive SoCs.
The primary objectives of this thesis will include:
- Translate automotive SoC requirements– BW/Latency, Memory hierarchy, FUSA, ADAS to chiplet and system architectures. Explore different connectivity options – monolithic, chiplet (2D, 2.5D, 3D).
- Design and implement an analysis framework that accurately models chiplet interactions and all blocks at the unit level.
- Evaluate the proposed framework using workloads (traffic generators, CPUs, GPUs) to quantify system-level performance for different architectures.
- Collaborate with our chiplet/system architects and R&D team to translate findings into practical solutions that can influence the design and application of chiplet technology.
Interested candidates are encouraged to apply and contribute to groundbreaking research that drives the future of semiconductor design.
About Us
Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software
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