Senior Digital Design Verification Engineer

il y a 6 jours


Leuven, Belgique microTECH Global LTD Temps plein

We have had a great opportunity for a Senior Digital Design Verification Engineer in Belgium. Job Title: Senior Digital Design Verification Engineer Location: Leuven, Belgium – minimum 3 days in office Type: Freelancer | 100% FTE (40 hours/week) Duration: 6 months Start Date: 12 Jan 2026 Hourly rate: €60–75/hour Key Skills: UVM SystemVerilog Assertion-Based Verification 5–10 years' experience in digital IC design/verification Role Overview: We are building a new product development team in Leuven and seek a skilled engineer in digital IC hardware verification. The role involves verifying blocks, subsystems, or top-level functions, developing testbenches, and collaborating with cross-functional teams to ensure product success. Responsibilities: Own verification of assigned blocks/subsystems Develop and implement testcases using SystemVerilog, UVM, Python, and assertions Maximize verification coverage and maintain regression suites Participate in design reviews, peer reviews, and root-cause analysis Collaborate with other teams (Analog, Firmware, Layout) Candidate Profile: Master's in Electronic/Electrical Engineering Proven experience delivering high-volume silicon Knowledge of low-power design techniques; audio/AI accelerators a plus Familiar with Cadence EDA tools, Synopsys Spyglass, VHDL/Verilog/SystemVerilog, Python Strong analytical, debugging, and hands-on skills Team player with excellent communication; fluent in English If you could be interested, please get in touch and share your CV with me tee@microtech-global.com



  • Leuven, Belgique microTECH Global LTD Temps plein

    We have had a great opportunity for a Senior Digital Design Verification Engineer in Belgium. Job Title: Senior Digital Design Verification EngineerLocation: Leuven, Belgium – minimum 3 days in officeType: Freelancer | 100% FTE (40 hours/week)Duration: 6 monthsStart Date: 12 Jan 2026Hourly rate: €60–75/hour Key Skills:UVMSystemVerilogAssertion-Based...


  • Leuven, Belgique microTECH Global LTD Temps plein

    We have had a great opportunity for a Senior Digital Design Verification Engineer in Belgium. Job Title: Senior Digital Design Verification EngineerLocation: Leuven, Belgium – minimum 3 days in officeType: Freelancer | 100% FTE (40 hours/week)Duration: 6 monthsStart Date: 12 Jan 2026Hourly rate: €60–75/hour Key Skills:UVMSystemVerilogAssertion-Based...


  • Leuven, Belgique microTECH Global LTD Temps plein

    We have had a great opportunity for a Senior Digital Design Verification Engineer in Belgium. Job Title: Senior Digital Design Verification EngineerLocation: Leuven, Belgium – minimum 3 days in officeType: Freelancer | 100% FTE (40 hours/week)Duration: 6 monthsStart Date: 12 Jan 2026Hourly rate: €60–75/hour Key Skills:UVMSystemVerilogAssertion-Based...


  • Leuven, Belgique ICsense NV Temps plein

    The job location can be Leuven or Ghent.The Senior Digital Design Engineer is responsible for the study, design and verification of high quality ICs, technical team lead in challenging projects and the coaching of junior engineers. Responsibilities Study, specification, design and verification of high-quality digital and mixed-signal ICs Write digital...


  • Leuven, Belgique Qplox engineering Temps plein

    Responsibilities:_Own the verification of a block, some subsystem part or some top level functions_Detail the verification specification of the assigned testcases_Implement the testcases using System Verilog, UVM, Python, assertions_Maximize the verification coverage of the design while focusing on execution time_Maintain the regression suite_Execute to meet...


  • Leuven, Belgique Qplox engineering Temps plein

    Responsibilities:_Own the verification of a block, some subsystem part or some top level functions_Detail the verification specification of the assigned testcases_Implement the testcases using System Verilog, UVM, Python, assertions_Maximize the verification coverage of the design while focusing on execution time_Maintain the regression suite_Execute to meet...


  • Leuven, Belgique Qplox engineering Temps plein

    Responsibilities:_Own the verification of a block, some subsystem part or some top level functions_Detail the verification specification of the assigned testcases_Implement the testcases using System Verilog, UVM, Python, assertions_Maximize the verification coverage of the design while focusing on execution time_Maintain the regression suite_Execute to meet...


  • Leuven, Belgique Qplox engineering Temps plein

    Responsibilities: _Own the verification of a block, some subsystem part or some top level functions _Detail the verification specification of the assigned testcases _Implement the testcases using System Verilog, UVM, Python, assertions _Maximize the verification coverage of the design while focusing on execution time _Maintain the regression suite _Execute...

  • Digital IC Verification

    il y a 3 semaines


    Leuven, Belgique Optimus Search Temps plein

    Digital IC Verification – Leuven – 6 Months - FREELANCE - ASAP Our client, based in Leuven, is looking for an experienced figure in the field of Digital IC Design & Verification. Requirements: Good experience in designing and/or verifying digital blocks and ICs. Familiarity with low-power design techniques. Demonstrated success in delivering working...


  • Leuven, Belgique Optimus Search Temps plein

    Digital IC Verification – Leuven – 6 Months - FREELANCE - ASAPOur client, based in Leuven, is looking for an experienced figure in the field of Digital IC Design & Verification.Requirements:Good experience in designing and/or verifying digital blocks and ICs.Familiarity with low-power design techniques.Demonstrated success in delivering working silicon...