Admittance Modeling Engineer Internship for Ge CFETs
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imec in Belgium offers a Master or PhD internship to develop and implement an admittance model for CFET gate stacks using Comphy, focusing on fitting experimental data and refining the approach.
The project emphasizes physics-based modeling of defect populations, temperature effects and parasitic contributions, aiming for robust, physically meaningful extraction in collaboration with imec's advanced semiconductor teams.
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Vlaams-Brabant, Vlaams-Brabant, Belgique Imec Temps plein 6 700 € - 11 000 € Contrat[NanoIC topic] Admittance modeling for scoping defects in advanced germanium Metal-Oxide-Semiconductor gate stacks for CFETSolve the characterization and modeling challenge enabling tomorrow’s CFET technologyCMOS scaling isentering the 3D era with complementary field-effect transistors (CFETs), inwhich n- and p-type devices are vertically stacked on top of...