Staff Layout Design Engineer — DDR/HBM IP
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Synopsys, Inc. is seeking an experienced memory-IP layout engineer to lead the DDR and HBM PHY layout across 7nm and below, in FinFET and GAA processes.
You will own floorplanning, layout execution, and design reviews for analog/mixed-signal blocks within memory PHY subsystems, and collaborate across circuit design, verification, and product engineering teams. You will mentor junior engineers, drive EMIR, PERC, DFM checks and LEF generation, estimate effort, plan schedules, and ensure
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