PhD in Quality-of-Service-Aware Architectures for Shared Memory Chiplets in Multi-Die Systems

Organisation/Company IMEC Research Field Engineering » Electrical engineering Computer science Researcher Profile First Stage Researcher (R1) Positions Master Positions Application Deadline 24 Oct 2026
- 23:59 (Europe/Brussels) Country Belgium Type of Contract To be defined Job Status Full-time Is the job funded through the EU Research Framework Programme? Not funded by a EU programme Is the Job related to staff position within a Research Infrastructure? No

Offer Description

This PhD research investigates how shared memory chiplet architectures can be designed to provide both scalability and predictable performance for safety-critical systems.

Imec Heilbronn is a new regional hub pioneering open chiplet architectures that will power the next generation of automotive innovation and AI‑driven systems. Situated at the heart of the Innovation Park Artificial Intelligence (IPAI), imec Germany brings together world class semiconductor expertise and a vibrant ecosystem of AI innovation. This unique combination positions the site as a catalyst for technological breakthroughs that will shape the next generation of mobility and intelligent systems.

The Advanced Chip Design Accelerator (ACDA) is the core of our mission in Heilbronn—establishing a state of the art competence center dedicated to advanced chiplet design, system integration, and cutting edge methodologies. ACDA provides the expertise and tools needed to bridge the gap between early stage research and industrial adoption, enabling faster, safer, and more scalable deployment of chiplet based technologies in the automotive domain. Building on the foundation of imec’s Automotive Chiplet Program (ACP), ACDA extends this work into a regional accelerator that translates imec’s research leadership into practical, industry ready solutions. By combining advanced design capabilities with deep local collaboration, ACDA empowers both regional and global automotive players to derisk development, accelerate innovation cycles, and industrialize next generation chiplet platforms with confidence.

What you will do

Introduction and Motivation

The transition from monolithic System-on-Chip (SoC) designs toward multi-die and chiplet-based architectures represents a fundamental shift in modern computing systems. In current chiplet architectures, memory access is typically handled via dedicated memory interfaces and controllers attached to each compute chiplet. While this approach preserves locality and simplifies design, it scales poorly as the number of chiplets increases in a system. Replicating memory interfaces leads to excessive IO requirements, increased area overhead, and inefficient memory utilization, particularly in tightly constrained environments such as automotive platforms. As applications demand higher compute density within a single package, the traditional model of per-chiplet memory integration becomes increasingly unsustainable.

A promising alternative is the introduction of shared memory chiplets, where memory resources are centralized and logically shared across multiple dies via high-speed die-to-die interconnects. This architectural shift reduces IO duplication and improves resource utilization but fundamentally changes the nature of memory access. Instead of isolated local memory, compute chiplets must now compete for access to a common memory resource, leading to contention and increased latency variability. These challenges are particularly critical in safety-critical domains such as automotive systems, where predictable performance and strict timing guarantees are essential.

This proposal addresses the central question of how to design shared memory chiplet architectures that remain scalable while providing strong Quality-of-Service (QoS) guarantees required for safety-critical applications.

Research Objectives

The main objective of this PhD is to develop architectural principles and mechanisms that enable predictable and efficient access to shared memory in multi-die systems. The research aims to bridge the gap between scalability and performance guarantees by introducing cross-layer QoS mechanisms spanning interconnects, memory hierarchies, and system-level scheduling. More specifically, the work will investigate how shared memory chiplet architectures can be designed such that multiple compute chiplets can concurrently access memory resources without violating latency or bandwidth constraints. The goal is not only to optimize average system performance but to ensure bounded worst-case behavior, which is essential for safety-critical applications.

Another key objective is to understand and formalize the interplay between die-to-die communication and memory system behavior. In shared memory chiplet systems, performance bottlenecks are no longer confined to either the interconnect or the memory controller alone; instead, they emerge from their interactio