Automated multi-constraint routing for spin-based quantum processor architectures

/ Automated multi-constraint routing for spin-based quantum processor architectures

Automated multi-constraint routing for spin-based quantum processor architectures

Master internship - Leuven | More than two weeks ago

This project will enable a scalable routing solution for spin-based quantum processors.

Advances in semiconductor quantumtechnologies increasingly rely on densely integrated arrays of gate-definedquantum dots for spin‑qubit processors. A critical bottleneck in scaling thesearchitectures is the automated routing of the complex, multi‑layer wiringnetworks required to interface nanoscale gate electrodes with micrometer‑scalecontact pads. This project aims to develop a high‑performance auto‑routingframework tailored to the unique constraints of quantum‑dot spin qubit devices.The student will investigate algorithmic strategies for simultaneously routinglarge numbers of wires that must remain non‑crossing, satisfy stringent spacingrules, and gradually transition in width by more than an order of magnitudealong their routing path, from tens of nanometers at the qubit layer to severalmicrometers at the periphery.

This project is at the intersection ofcomputational optimization and state-of-the-art quantum-processor design in collaborationwith the spin-qubit research group at imec.

Emphasis will be placed on modelingmanufacturability constraints, developing efficient search heuristics, andvalidating routing performance on realistic quantum‑processor layouts.

Type of internship: Master internship

Duration: Up to one academic year

Required educational background: Computer Science, Other

The reference code for this position is 2026-INT-151. Mention this reference code in your application.

Only for self-supporting students.

Advances in semiconductor quantumtechnologies increasingly rely on densely integrated arrays of gate-definedquantum dots for spin‑qubit processors. A critical bottleneck in scaling thesearchitectures is the automated routing of the complex, multi‑layer wiringnetworks required to interface nanoscale gate electrodes with micrometer‑scalecontact pads. This project aims to develop a high‑performance auto‑routingframework tailored to the unique constraints of quantum‑dot spin qubit devices.The student will investigate algorithmic strategies for simultaneously routinglarge numbers of wires that must remain non‑crossing, satisfy stringent spacingrules, and gradually transition in width by more than an order of magnitudealong their routing path, from tens of nanometers at the qubit layer to severalmicrometers at the periphery.

This project is at the intersection ofcomputational optimization and state-of-the-art quantum-processor design in collaborationwith the spin-qubit research group at imec.

Emphasis will be placed on modelingmanufacturability constraints, developing efficient search heuristics, andvalidating routing performance on realistic quantum‑processor layouts.

Type of internship: Master internship

Duration: Up to one academic year

Required educational background: Computer Science, Other

Supervising scientist(s): For further information or for application, please contact Jacques Van Damme (Jacques.VanDamme@imec.be ) and Clement Godfrin (Clement.Godfrin@imec.be )

The reference code for this position is 2026-INT-151. Mention this reference code in your application.

Only for self-supporting students.