Memory Behavior Analysis in Accelerator-Centric Computing Systems and Chiplet-based Architectures
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Memory Behavior Analysis in Accelerator-Centric Computing Systems and Chiplet-based Architectures
Investigate how memory architecture influences performance, power consumption, and thermal behavior in accelerator-driven workloads.
This internship aims to study memory behavior under realistic AI workloads. Integrating a DRAM simulator with an AI accelerator in a chiplet system, the work enables end-to-end analysis of accelerator-generated memory traffic and its impact on DRAM performance, command activity, power consumption, and thermal behavior. Beyond establishing the integration itself, the internship will investigate how workload characteristics, memory configurations, and DRAM technologies influence system efficiency, providing a foundation for future research on memory-aware accelerator and chiplet-based system design.
Type of internship: Master internship
Duration: 4 months
Required educational background: Electrotechnics/Electrical Engineering, Computer Science
The reference code for this position is 2026-INT-294. Mention this reference code in your application.
Imec allowance will be provided.