Senior Digital Verification Engineer
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EURAXESS Czech Republic is offering a position focused on the design of complex System on Chips (SoCs) in Heverlee, Belgium. Ideal candidates will have substantial experience in digital circuit verification using SystemVerilog/UVM, along with scripting in TCL and Python, enabling them to contribute effectively to a leading research center.
The role emphasizes collaboration within interdisciplinary teams and includes opportunities for development in a multicultural, supportive environment with a market-competitive salary and benefits.