Senior Digital Verification Engineer

Il y a 1 jour

Heverlee, Vlaams-Brabant, Belgique EURAXESS Czech Republic Temps plein 55 000 € - 70 000 € Contrat

EURAXESS Czech Republic is offering a position focused on the design of complex System on Chips (SoCs) in Heverlee, Belgium. Ideal candidates will have substantial experience in digital circuit verification using SystemVerilog/UVM, along with scripting in TCL and Python, enabling them to contribute effectively to a leading research center.

The role emphasizes collaboration within interdisciplinary teams and includes opportunities for development in a multicultural, supportive environment with a market-competitive salary and benefits.