Senior Digital Design Engineer — SoC Power

Cyient Limited in Belgium is seeking a Digital Design engineer to transform imaginative ideas into high-performance RTL/SoC IPs for RF CMOS and high-speed data communication. You will define micro-architecture, develop RTL using SystemVerilog/Verilog/VHDL, and drive low-power design.

Collaboration with verification and backend teams is essential to meet timing and power goals, while strong communication skills support cross-functional work. Minimum qualifications include a B.S./M.S.