Senior Digital Verification Engineer, Crypto
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We Are Actively Expanding The Crypto & Security Competence Centre (CCC&S) At NXP And We Have New Opportunities In Our Team For Digital Verification Engineers Working On Next-generation Security Technologies Such As
- Post-Quantum Cryptography (PQC) IP
- Secure SoC subsystems, including next-generation roots of trust
- High-assurance cryptographic accelerators for future platforms
Driven Verification – What You’ll Be Part Of
- AI-driven verification automation – reducing regression effort while maintaining full coverage
- Intelligent debug and analysis – accelerating bug discovery and root-cause identification
- Automated test and vPlan generation – improving consistency and reducing human error
We Are Also Actively Developing Advanced Capabilities Including
- AI-assisted RTL understanding and test explanation
- Conversational debug interfaces for waveform and design interaction
- AI-driven coverage closure and test prioritization
What You’ll Be Doing
- Lead the verification of advanced PQC and security IP, tackling complex, security-focused design challenges
- Define and drive verification strategy, leveraging AI and automation to enhance productivity and quality
- Architect and scale SystemVerilog/UVM verification environments for IP and subsystem-level validation
- Champion Constrained Random and Metrics-Driven Verification (MDV) methodologies
- Own and drive coverage closure, using data-driven insights for high-confidence sign-off
- Develop SystemVerilog Assertions (SVA) for protocol checking and early defect detection
- Collaborate closely with design and architecture teams to influence verification from early stages
- Mentor and support engineers, contributing to a high-performing and forward-looking team culture
Why This Role Stands Out
- Work on cutting-edge cryptography technologies critical to future cybersecurity
- Help define how AI transforms verification workflows and methodologies
- Join a growing organisation where your input shapes tools, processes, and technical direction
- Take ownership of high-visibility, complex projects from concept to silicon
Your Profile
- BSc., or MSc., degree in Electronics or Electrical Engineering.
- Strong hands-on experience with SystemVerilog for testbench development and verification.
- Proven expertise in UVM (Universal Verification Methodology), including component creation, sequences, drivers, monitors, and scoreboards.
- Solid understanding and practical use of Constrained Random Verification techniques.
- Experience with Metrics‑Driven Verification, including functional coverage and verification planning.
- Ability to write SystemVerilog Assertions (SVA) for protocol and design checking.
- Demonstrated success in achieving Coverage Closure across functional and code coverage metrics.
- Experience analysing coverage results and refining test strategies to close gaps.
- Strong debugging skills across simulations and complex verification environments.
- Knowledge of Formal Verification methods would be advantageous.
Remote / Hybrid working is applicable to this position.
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