Foundation Models, World Models and Continual Learning for Semiconductor Lithography and Metrology: Advancing Machine Learning towards High-NA EUV Process Control

Foundation Models, World Models and Continual Learning for Semiconductor Lithography and Metrology: Advancing Machine Learning towards High-NA EUV Process Control

Teaching machines to predict what will print

As patterning moves to high-NA EUV lithography, process windows shrink. Thinner resists produce noisier, lower-contrast SEM images, and stochastic failures (missing contacts, micro-bridges, line breaks) become a dominant yield limiter. Today, computational lithography (OPC, process simulation), metrology and defect inspection are handled as separate problems. Each relies on its own task-specific models, large amounts of labelled data and frequent recalibration. None of them builds a shared, transferable understanding of how design intent, process conditions and measured outcomes relate to each other.

Recent advances in machine learning offer a way to change this. Transformer-based foundation models, Joint-Embedding Predictive Architectures (I-JEPA, V-JEPA), latent world models and continual learning methods can learn from large amounts of unlabelled data, predict outcomes under changing conditions, and adapt to new tasks without retraining from scratch. Semiconductor manufacturing is a demanding testbed for these methods. Its data are noisy, scarce in labels, multi-modal and governed by physics that is only partially known, and it requires nanometre-level accuracy.

This Master’s internship advances these methods in that setting. The semiconductor process flow sets the boundary conditions and evaluation criteria. Depending on the candidate’s profile, the thesis will focus on one or more of the following research directions:

• Self-supervised foundation models for metrology images: pretraining transformer and JEPA-style encoders on large unlabelled SEM/TEM datasets, and studying representations that hold up under low dose, low contrast and anisotropic noise.
• World models of the patterning process: learning action-conditioned latent models that predict the measured outcome from design (layout/GDS) and process conditions (dose, focus, illumination, mask bias). This enables counterfactual “what-if” analysis across the process window.
• Label‑free and few‑shot defect detection: detecting rare, novel and stochastic defects through prediction error, density modelling or few‑shot learning, with calibrated uncertainty.
• Continual learning across layers, tools and nodes: adapting models to new data distributions without catastrophic forgetting, and quantifying how many labelled samples each new task requires.
• Machine learning for computational lithography: fast learned surrogates for lithography simulation, ML-assisted OPC/inverse lithography, and learned mask/process correction, benchmarked against conventional rigorous methods.
• Multi-modal, uncertainty‑aware learning: combining metrology images, layout and tool/process data into representations that support reliable process control decisions.

By tackling these challenges, the project aims to advance the state of the art in representation learning, predictive modelling and adaptation under strict noise, data and accuracy constraints. The findings should apply beyond semiconductor manufacturing to other scientific and industrial imaging domains.

The selected intern/student will learn the conventional patterning process flow. They will work collaboratively on developing and applying machine‑learning-based algorithms with four goals: 1) reducing computational cost compared to rigorous simulation, 2) reducing tool cycle time and metrology sampling, 3) enabling a predictive process control approach for advanced‑node manufacturing, and 4) improving the quality and information content of metrology data.

Machine learning applicability includes:

1. Technical diligence: scope the research question, model choice, compute budget and evaluation protocol to meet the target performance and timeline.
2. Data curation and analysis: collect and analyse image data (SEM/TEM/EDR/…), layout clips and process/tool data. Formulate hypotheses in a feedback loop with domain experts.
3. Model development: build new architectures or substantially improve existing ones (transformers, JEPA, world models, continual learning, generative models) for the chosen task, with a focus on methodological contribution.
4. Rigorous evaluation: benchmark against strong baselines, with ablations, uncertainty quantification and analysis of generalization across data distributions.
5. Dissemination: collaborate on publications targeting top‑tier machine learning and computer vision venues (CORE A*/A), such as NeurIPS, ICML, ICLR, CVPR, ICCV and ECCV, and high‑impact journals such as IEEE TPAMI, IJCV and TMLR.

We offer a fully funded internship scholarship (subject to conditions) for a maximum