Frontend RTL Designer for SoC
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Vertical Compute is seeking a Front-End RTL Designer to contribute to building our 3D-integrated chiplets and AI accelerator platforms. You will lead top-level SoC/chiplet integration, collaborating with verification and physical design teams to achieve target PPA metrics.
You should have a solid background in front-end RTL design (SystemVerilog/Verilog) and experience integrating IP blocks into unified silicon architectures, working in a fast-paced, collaborative hardware environment.