Lead RTL Verification Engineer for AI Chiplets

Vertical Compute is seeking an RTL Verification Engineer to lead verification of our 3D-integrated chiplets, focusing on top-level validation of the chiplets and their tight coupling with the VIM memory technology. You will work with Front-End RTL Design, System Architecture and Software teams to ensure tape-out readiness.

The role requires strong SystemVerilog/UVM expertise, a track record in ASIC/SoC verification, and excellent collaboration and English communication.