Senior DFT Engineer: SoC Test
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IMEC in Leuven, Belgium, seeks a Senior DFT Engineer to design and implement advanced test solutions for SOCs and multi-block chips in a world-leading R&D environment.
You will collaborate with physical design and test teams to define DFT flows, insert techniques, and validate fault coverage across 5nm+ nodes, leveraging state-of-the-art EDA tools and scripting. The role offers growth within a premier nanotechnology center.