Digital Designer — CPU Subsystem

h3Digital Designer — CPU Subsystem (RTL Verification) (Temporary Assignment) /h3 pCompute System Architecture (CSA) is imec's center of excellence for hardware-software-technology co-design of future compute systems. We work in close collaboration with imec's expertise centers in applications, technology, circuits, and design to innovate and pathfind next-generation compute architectures across AI, HPC, automotive, space, and other domains. CSA operates across six imec centers — Belgium, the Netherlands, Germany, the UK, the USA, and Qatar. This position is based primarily in Leuven, Belgium. /p pWe are looking for a Digital Designer to join the Platform, Prototypes and Physical-Aware Design (P3D) group, with a focus on the CPU subsystem of imec's RISC‑V-based compute platforms. You will own RTL design of CPU‑side blocks — pipelines, caches, memory hierarchy, and the surrounding interconnect logic — and drive their verification from unit‑level testing through subsystem‑level integration. /p pYour work directly feeds imec's prototype demonstrators, the silicon vehicles for imec's bCMOS 2.0 /b vision: functionally partitioned, 3D‑integrated compute systems that push well beyond what monolithic SoCs can deliver. You will work on technology beyond 2nm, alongside principal SoC and chiplet architects, in a fast‑moving research environment with high industrial visibility. /p h3What you will do /h3 ul liTranslate microarchitectural specifications into clean, synthesizable RTL (SystemVerilog) for CPU subsystem blocks — front‑end, execution pipeline, load/store unit, caches, and on‑chip memory interfaces. /li liIntegrate RISC‑V cores with surrounding subsystem components: cache hierarchies, coherency logic, AXI/CHI interconnects, and debug/trace infrastructure. /li liDevelop and execute functional verification environments for the modules you design — testbenches, UVM agents, SystemVerilog assertions, coverage models — and drive coverage closure to tape‑out quality. /li liCollaborate closely with SoC and chiplet architects to refine specifications, resolve ambiguities, and feed implementation insights back into the architecture loop. /li liAnticipate PPA, timing, and floorplan implications in your RTL, supporting physical‑aware design iterations through to prototype tape‑out. /li liContribute to verification IP, regression infrastructure, and design/verification flow improvements used across the group. /li liDocument design and verification intent clearly enough that the next engineer — or the next prototype — can build on it. /li liThis is a temporary contract of two years, with the possibility to extend the contract. /li /ul h3What we do for you /h3 pWe offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will determine the society of tomorrow. /p pWe are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth. /p pWe are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits. /p h3Who you are /h3 ul liAt least 5 years of hands‑on RTL design experience in SystemVerilog/Verilog for CPU, GPU, or similarly complex digital subsystems. /li liSolid grasp of CPU microarchitecture — pipelines, hazards, branch prediction, caches, memory ordering — at a level that lets you read an architectural spec and turn it /li liinto RTL with sound design choices. /li liStrong functional verification capability: UVM, SystemVerilog assertions (SVA), coverage‑driven verification, constrained‑random stimulus, and debug discipline. /li liFamiliarity with one or more standard interconnect protocols (AXI, ACE, CHI, TileLink) at both RTL and verification level. /li liHands‑on experience with industry EDA flows (Synopsys, Cadence, Siemens) for simulation, lint, CDC, and synthesis. /li liComfort with scripting (Python, Tcl, Make) for verification automation, regressions, and design integration. /li liExcellent written and spoken English, with the documentation habits to match. /li liA structured, transparent way of working and a collaborative attitude in a multidisciplinary, multicultural team. /li /ul pConsidered an asset: /p ul liExperience with RISC‑V cores (in‑order or out‑of‑order) at RTL level. /li liExposure to formal verification methods and tools. /li liFamiliarity with High‑Level Synthesis (HLS) flows and inte