Physical ASIC Design Implementation Engineer

pOrganisation/Company IMEC Research Field Technology » Nanotechnology Researcher Profile Other Profession Positions Master Positions Application Deadline 21 Nov 2026
- 23:59 (Europe/Brussels) Country Belgium Type of Contract Permanent Job Status Full-time Is the job funded through the EU Research Framework Programme? Not funded by a EU programme Is the Job related to staff position within a Research Infrastructure? No /ph3Offer Description /h3pAs Physical ASIC design engineer within DSRD, you will be in direct contact with our customers for future projects. You will have full understanding of the complete Cadence Innovus PlaceRoute flow. /ph3What you will do /h3pFor more than 25 years, imec has been offering an ASIC prototyping and production service to worldwide companies. Imec helps its customers to design their integrated circuits (chips) and bring them from the prototype to the production stage. Our list of customers includes more than 900 universities and companies worldwide. For the further extension of the physical digital implementation group (Back-End group) in DSRD, we are looking for a highly motivated engineer. /ppDSRD, as part of imec, has an extensive industrial experience, contacts with leading industrial foundries, and long-standing relationships with all the main EDA tool vendors and IP providers. This unit supports worldwide customers in the layout, prototype, fabrication and test of advanced electronic products. /ppAs Physical ASIC design engineer within DSRD, you will be in direct contact with our customers for future projects. You will have full understanding of the complete Cadence Innovus PlaceRoute flow: /pulliSet up the flow for the specific library set and foundry node used /liliSet up low power design (UPF) /liliFloorplanning power grid design /liliDetailed Timing Driven Placement /liliClock Tree Synthesis /liliScan chain re-stitching /liliDetailed Timing Driven Route (incl. SI) /liliIPO’s (in-place optimization) to get the timing in all corners correct /liliSolve setup hold violations /liliSign-off extraction (SPEF/QUANTUS) /liliSign-off timing (TEMPUS) /liliSign-off Power analysis (VOLTUS) /liliPhysical verification (DRC, ERC, LVS, ANT) /liliLogic equivalent check /li /ulpFor hierarchical designs you can take the lead for partitioning and split the top level SDC file into timing budget requirements/constraints of the sub-blocks. You will work directly with the Physical Design implementation team during the entire chip design cycle to drive signoff closure for tape-out, You are also the technical voice to the customer to discuss his specifications. /pulliYou have at least 8 years of experience in physical implementation in advanced nodes (12 – 5nm) and hierarchical designs. /liliYou have experience in power reduction techniques like gated clocks, voltage domains, memory retention and switch off power domains. /liliYou have experience in debugging any tool/flow/design issue. /liliYou have excellent communication skills (English is a must) and can work within an international team. /liliYou like to interact with customers. /li /ulpLanguages ENGLISH Level Excellent /ppResearch Field Technology /ph3Additional Information /h3h3What we do for you /h3pWe offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its office in Leuven. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will define the society of tomorrow. /ppWe are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth. /ppWe are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits. /p