Physical ASIC Design Implementation Engineer

Il y a 5 heures

Flemish Brabant, Flanders, Belgique VeroTech Temps plein
ppJoin our innovative team as a Physical ASIC Design Implementation Engineer, where you'll work on cutting-edge projects spanning a range of technologies from N2 to 180nm. Leverage your expertise in the full backend process, from netlist to GDSII-out, and become an integral part of advancing our client’s technological capabilities. /ph3About The Role /h3pAs a Physical ASIC Design Implementation Engineer, you will be involved in a dynamic environment working on top-level chips and block-level designs. You will be responsible for managing direct communication with clients, tailoring solutions to their specifications, and ensuring seamless execution throughout the design cycle with full Cadence Innovus PlaceRoute flow understanding. Your role will involve partitioning tasks, driving signoff closure, and leading technical discussions. /ph3Key responsibilities /h3ulliLiaise with customers for future project specifications and execution /liliDemonstrate full proficiency in Cadence Innovus PlaceRoute flow /liliLead partitioning and division of the top-level SDC file into timing constraints for sub-blocks /liliCollaborate with the Physical Design implementation team for signoff closure. /liliManage technical communication with customers regarding their specifications /liliSet up flows for specific library sets and foundry nodes /liliDevelop low power designs (UPF) and debug SDC files /liliExpertise in Floorplanning power grid /lilidesign for top-level and block-level tasks /liliConduct Placement, CTS Routing, and solve setup hold violations /liliExecute sign-off extraction, timing, and power analysis /liliPerform physical verification, equivalence checks, and more /li /ulh3What we're looking for /h3ulliWe seek a skilled professional with a strong background in physical ASIC design implementation and experience in Cadence Innovus PlaceRoute flow /liliExcellent understanding of chip design from netlist to GDSII-out /liliProven ability in partitioning and dividing top-level data into sub-block constraints /liliExperience with low power design and SDC file debugging /liliFamiliarity with various verification methods and sign-off processes /li /ulpAt VeroTech, we empower engineers to grow, innovate, and lead. Join a dynamic community where you’ll work on cutting-edge RD projects, receive personalized career development, and thrive in a supportive, inclusive culture. Enjoy flexibility with remote work options, a competitive salary package, and additional benefits like meal vouchers, insurance, and a company car. Be part of impactful projects that shape the future of technology while maintaining a healthy work-life balance. /ph3Benefits /h3ulliflexibility with remote work options /lilicompetitive salary package /lilimeal vouchers /liliinsurance /lilicompany car /li /ulpReady to inspire? /p /p