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We are looking for an experienced FPGA Design & Validation Engineer to join our hardware development team. You will take ownership of the complete FPGA flow, from RTL design through implementation, prototyping, and electrical validation, working closely with another FPGA expert in a highly hands-on lab environment. This role is ideal for an independent, detail-oriented engineer who thrives on solving complex timing, integration, and hardware validation challenges. ResponsibilitiesDrive the full FPGA development flow: RTL → Synthesis → Place & Route → Bitstream generation → Board validationAdapt and implement designs for FPGA prototypingDevelop and maintain timing constraints and analyze timing reports in collaboration with the design teamEnsure timing closure and resolve issues related to:Clock domain crossings (CDC)Clock generationCombinational loopsDevelop RTL in VHDL / Verilog / SystemVerilogPerform FPGA and board bring-up, debug, and validationCreate C-based test software for FPGA testingDevelop supporting Python tools and scriptsUse FPGA debug tools for root cause analysisConduct device and board-level electrical validationPerform hands-on bench validation using oscilloscopes and logic analyzersWork with revision control systems and manage compute jobsRequirementsMaster's degree (or equivalent experience) in Electrical Engineering, Computer Engineering, or related fieldStrong experience with Xilinx FPGA flowProven experience with:Synplify (synthesis)Vivado Place & RouteDeep understanding of digital design principlesSolid expertise in timing analysis and closureExperience with hardware debug & electronics fundamentalsProficiency in C and Python developmentAbility to work independently and take technical ownershipStrong problem-solving and lab debugging skillsNice to HaveExperience with large-scale FPGA prototyping platformsAutomated test frameworksHigh-speed interfaces or complex SoC integrationCI/CD or scripted FPGA flowsLocation and Joining date: Belgium and We are searching for candidates who can move in a timeframe of below 1 month
