Full Custom ASIC Analog Layout Engineer
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• Design Analog Layouts like PLL, BG, LVDS, IVREF etc. for various projects for Space Application and various other Research projects at Imec.
• Perform physical verifications like DRC, LVS, EM/IR and other applicable checks for the designed blocks.
• Perform floorplan and top-level routing, keeping in mind the various power domains, and various challenges associated with mixed signal design.
• Perform all CHIP level validations post Dummy fill and other sign-off checks necessary for the tape-out.
• Provide all the deliverables in time to meet the Project deadlines.
• Archival of all the reports and checklists at the end of the Project.
• Contribute various Layout guidelines, checklists and other documents for various Technology nodes. What we do for you
We offer
you the opportunity to join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will determine the society of tomorrow. We are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth. We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits. Who you are
• You have a master’s degree (or equivalent through experience) in Electronics or Electrical Engineering.
• You have experience in designing various Analog Blocks and for Top Level integration of these blocks and signoff checks.
• Knowledge to design layouts in FINFETs and other advanced SOI nodes will be an added advantage.
• You must have sound knowledge of EDA Tools.
• Understanding of Layout Dependent Effects for deep submicron technology nodes.
• Tape-out experience in advanced process technology nodes is preferable.
• Knowledge about Radiation Hardening and its implementation in Layouts.
• Knowledge about svn, cliosoft or any other versioning tools.
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