Physical ASIC Design Implementation Engineer
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Job Description
Physical Implementation engineer for full backend (P&R) projects from netlist-in to GDSII-out flow, for toplevel chips aswell as blocklevel blocks in technologies ranging from N2 to 180nm. This with the full understanding of the complete Cadence Innovus Place&Route flow. Direct contact with our customers for future projects. Full understanding of the complete Cadence Innovus Place&Route flow. Take the lead for partitioning and split the top level SDC file into timing budget requirements/constraints of the sub-blocks. Work directly with the Physical Design implementation team during the entire chip design cycle to drive signoff closure for tape-out. Technical voice to the customer to discuss his specifications 📚 Profile / Requirements Experience in setting-up the flow for the specific library set and foundry node used Experience in setting-up low power design (UPF) and debug sdc file Knowledge in Floorplanning & power grid design for toplevel aswell as blocks Place, CTS & Routing Solve setup & hold violations Sign-off extraction (SPEF/QUANTUS) , timing (TEMPUS), Power analysis (VOLTUS) Physical verification (DRC, ERC, LVS, ANT), Logic equivalent check 🌟 Why join us ?
We offer
you a position as a consultant within the fascinating world of high tech and innovation. We provide a complete package with on one side training, coaching and a close follow-up, and on the other side a balanced salary package with fringe benefits based on your capabilities and experience. Working with us means choosing a long-term perspective, development possibilities, and a personal approach. A human-centered, diverse company that values and supports your physical and mental well-being.
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