Junior Digital IC Layout
Il y a 3 heures
Flemish Brabant, Flanders, Belgique
ICsense
Temps plein
Gratuit avec email ou Google
Enregistrez cette offre et organisez votre recherche
Créez un compte gratuit pour enregistrer des offres d'emploi, créer des alertes et revenir à cette liste depuis votre tableau de bord.
Gratuit avec email ou Google
En continuant, vous acceptez nos Conditions d’utilisation & Politique de confidentialité.
pHome
- Careers
- Junior Digital Physical Design / PnR Engineer /ph3Junior Digital Physical Design / PnR Engineer /h3pThe job location is Leuven. /ppstrongThe main role of the junior digital physical design / PnR Engineer is to perform and organize the digital and mixed-signal physical design of ASICs developed by ICsense. /strong /ph3Responsibilities /h3pPhysical design of digital integrated circuits (place route) following the internal design rules and quality regulations. Assumes full responsibility on the quality and accurateness of the back-end layouts. /pulliIn close cooperation with analog layouters, digital designers and project leaders /liliOrganization of deliverables and timings of these deliverables to ensure high-quality and timely delivery of the digital and mixed-signal top-level layout /liliTop-level assembly of ASICs containing digital and analog parts, considering DFT /liliSetup and maintain technology setup and tool flow for place route and physical synthesis /li /ulh3Competences /h3ulliYou have a master’s degree in electrical engineering (preferably chip design) /liliYou are a dynamic and highly motivated engineer /liliYou want to learn all about digital physical design, floor planning and PR for multiple power-domains (UPF) and multiple clock-domains. /liliYou love automating tools using e.g. a script-based approach (Python, TCL…) to streamline the back-end flow. /liliYou are interested to learn about digital synthesis, logic equivalence checking, Static Timing Analysis and physical verification. /liliYou have strong communication and reporting skills, also in English. /liliConsidered as a plus:ulliExperience with front-end RTL design in VHDL and/or Verilog and/or SystemVerilog /liliExperience with scripting and programming languages such as Python, TCL and C /liliExperience with back-end synthesis and timing analysis (STA) /li /ul /li /ulh3Our offer /h3ulliThe job location is Leuven /liliAn attractive salary package with a variety of extra benefits /liliA stimulating and pleasant working environment with regular team activities /liliA financially healthy company with growth potential /liliPossibility to continuously learn and grow through in-house and external trainings /liliBecoming a part of next generation innovative IC developments for international customers in micro-electronics, automotive, medical and industrial companies /li /ulThink you’d be a great addition to our team? We’d love to hear from you – get in touch and let’s start the conversation.pI want to contribute to making the world a better place and improving people's lives /p
- Careers
- Junior Digital Physical Design / PnR Engineer /ph3Junior Digital Physical Design / PnR Engineer /h3pThe job location is Leuven. /ppstrongThe main role of the junior digital physical design / PnR Engineer is to perform and organize the digital and mixed-signal physical design of ASICs developed by ICsense. /strong /ph3Responsibilities /h3pPhysical design of digital integrated circuits (place route) following the internal design rules and quality regulations. Assumes full responsibility on the quality and accurateness of the back-end layouts. /pulliIn close cooperation with analog layouters, digital designers and project leaders /liliOrganization of deliverables and timings of these deliverables to ensure high-quality and timely delivery of the digital and mixed-signal top-level layout /liliTop-level assembly of ASICs containing digital and analog parts, considering DFT /liliSetup and maintain technology setup and tool flow for place route and physical synthesis /li /ulh3Competences /h3ulliYou have a master’s degree in electrical engineering (preferably chip design) /liliYou are a dynamic and highly motivated engineer /liliYou want to learn all about digital physical design, floor planning and PR for multiple power-domains (UPF) and multiple clock-domains. /liliYou love automating tools using e.g. a script-based approach (Python, TCL…) to streamline the back-end flow. /liliYou are interested to learn about digital synthesis, logic equivalence checking, Static Timing Analysis and physical verification. /liliYou have strong communication and reporting skills, also in English. /liliConsidered as a plus:ulliExperience with front-end RTL design in VHDL and/or Verilog and/or SystemVerilog /liliExperience with scripting and programming languages such as Python, TCL and C /liliExperience with back-end synthesis and timing analysis (STA) /li /ul /li /ulh3Our offer /h3ulliThe job location is Leuven /liliAn attractive salary package with a variety of extra benefits /liliA stimulating and pleasant working environment with regular team activities /liliA financially healthy company with growth potential /liliPossibility to continuously learn and grow through in-house and external trainings /liliBecoming a part of next generation innovative IC developments for international customers in micro-electronics, automotive, medical and industrial companies /li /ulThink you’d be a great addition to our team? We’d love to hear from you – get in touch and let’s start the conversation.pI want to contribute to making the world a better place and improving people's lives /p