Senior Digital FE Design Engineer

Il y a 6 heures

Brussels, Brussels, Belgique EURAXESS Ireland Temps plein

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Offer Description

Senior Digital Front-End Design Engineer – Drive the complete RTL-to-GDS flow and shape next-generation silicon solutions. What you will do

As a Senior Digital Front-End Design Engineer, you are responsible for all design tasks in the RTL-to-GDS flow, ensuring high-quality and efficient implementation of complex ASIC designs. You work in a highly skilled Front-End (FE) team that provides design services to both internal IMEC research groups and external customers worldwide. The team consists of 10 members with diverse experience levels ranging from 2 to 35 years, offering a collaborative environment for knowledge sharing and technical growth. Perform

RTL synthesis

and optimize for timing, area, and power. Execute

DFT (Design-for-Test) insertion

using industry-standard tools. Conduct

Logical Equivalence Checking (LEC)

to validate design integrity. Generate and validate

ATPG (Automatic Test Pattern Generation)

patterns. Improve

test coverage

through advanced methodologies. Run

pre-layout and post-layout test pattern simulations

to ensure robustness. Collaborate closely with physical design teams for seamless RTL-to-GDS integration. Utilize

Cadence EDA tools

for synthesis, verification, and sign-off. Apply

Tessent (Siemens)

tools for DFT insertion and ATPG in specific projects. Troubleshoot and resolve design issues across the front-end flow. Document design processes and contribute to continuous improvement initiatives. Engage with internal and external stakeholders to deliver high-quality design services. Qualifications

5+ years of experience

in ASIC front-end design, including RTL-to-GDS flow. Proven expertise in

synthesis, DFT, LEC, ATPG

, and test coverage improvement. Hands‑on experience with

Cadence tools

(Genus, Modus, Conformal, etc.). Familiarity with

Tessent tools

for DFT and ATPG. Solid understanding of

digital design principles

, timing closure, and test strategies. Proficiency in

Verilog/SystemVerilog

and scripting languages (Tcl, Python, etc.). Strong problem‑solving skills and ability to work in cross‑functional teams. Excellent communication skills and attention to detail. A degree in

Electrical Engineering, Computer Engineering, or related field

(Master’s preferred). Languages

English – Excellent

Senior Digital FE Design Engineer

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Senior Digital FE Design Engineer

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