Senior Digital FE Design Engineer

ph3Offer Description /h3 pSenior Digital Front-End Design Engineer – Drive the complete RTL-to-GDS flow and shape next-generation silicon solutions. /p h3What you will do /h3 pAs a Senior Digital Front-End Design Engineer, you are responsible for all design tasks in the RTL-to-GDS flow, ensuring high-quality and efficient implementation of complex ASIC designs. You work in a highly skilled Front-End (FE) team that provides design services to both internal IMEC research groups and external customers worldwide. The team consists of 10 members with diverse experience levels ranging from 2 to 35 years, offering a collaborative environment for knowledge sharing and technical growth. /p ul liPerform bRTL synthesis /b and optimize for timing, area, and power. /li liExecute bDFT (Design-for-Test) insertion /b using industry-standard tools. /li liConduct bLogical Equivalence Checking (LEC) /b to validate design integrity. /li liGenerate and validate bATPG (Automatic Test Pattern Generation) /b patterns. /li liImprove btest coverage /b through advanced methodologies. /li liRun bpre-layout and post-layout test pattern simulations /b to ensure robustness. /li liCollaborate closely with physical design teams for seamless RTL-to-GDS integration. /li liUtilize bCadence EDA tools /b for synthesis, verification, and sign-off. /li liApply bTessent (Siemens) /b tools for DFT insertion and ATPG in specific projects. /li liTroubleshoot and resolve design issues across the front-end flow. /li liDocument design processes and contribute to continuous improvement initiatives. /li liEngage with internal and external stakeholders to deliver high-quality design services. /li /ul h3Qualifications /h3 ul lib5+ years of experience /b in ASIC front-end design, including RTL-to-GDS flow. /li liProven expertise in bsynthesis, DFT, LEC, ATPG /b, and test coverage improvement. /li liHands‑on experience with bCadence tools /b (Genus, Modus, Conformal, etc.). /li liFamiliarity with bTessent tools /b for DFT and ATPG. /li liSolid understanding of bdigital design principles /b, timing closure, and test strategies. /li liProficiency in bVerilog/SystemVerilog /b and scripting languages (Tcl, Python, etc.). /li liStrong problem‑solving skills and ability to work in cross‑functional teams. /li liExcellent communication skills and attention to detail. /li liA degree in bElectrical Engineering, Computer Engineering, or related field /b (Master’s preferred). /li /ul h3Languages /h3 pEnglish – Excellent /p /p