Senior Digital Design Engineer
Il y a 3 heures
belgium belgium
Cyient Limited
Temps plein
Gratuit avec email ou Google
Enregistrez cette offre et organisez votre recherche
Créez un compte gratuit pour enregistrer des offres d'emploi, créer des alertes et revenir à cette liste depuis votre tableau de bord.
Gratuit avec email ou Google
En continuant, vous acceptez nos Conditions d’utilisation & Politique de confidentialité.
pDo you have a passion for building entirely new solutions? As part of our Digital Design team, you’ll take imaginative ideas and turn them into reality. /p h3Responsibilities /h3 ul liMicro-architecture definition for efficient and power-optimized architectures /li liRTL development using System Verilog, or Verilog, VHDL /li liLow-power design (UPF) /li liLint, CDC/RDC /li liSynthesis constraining /li liSoft and hard IP identification, selection and integration /li liCollaboration with verification team in verification plan development and debug /li liCollaboration with backend team to close the design on timing and power /li /ul h3Minimum Qualification /h3 ul liB.
S. or M.
S. degree in Electrical Engineering, Computer Engineering or Computer Science with min. 4 years of experience in digital design /li liStrong communication and presentation skills /li liProactive mindset, strong problem solving skills, ability to work autonomously /li liKnowledge of RTL design /li liKnowledge of Testbench development /li liKnowledge of System Verilog and VHDL, Verilog /li /ul h3Preferred Qualification /h3 ul liKnowledge of mixed signal concepts /li liExperience in data path development h3Preferred Qualification /h3 ul liExperience in SoC architectures incl. CPU (ARM), Memory and Peripheral Subsystems /li liExperience with Synthesis, Timing Closure /li liExperience with Power Analysis and Optimization /li liExperience in Formal Verification Methodology /li liExperience in advanced Functional Verification Mythologies, i. e. UVM, Coverage modeling /li lixperience with scripting languages (TCL, Python, Perl, Shell-scripting) /li /ul pDesigns advanced digital and mixed-signal IPs and integrates on SoC for RF CMOS, high-speed data communication, data acquisition and low-power low-voltage applications. /p /li /ul
S. or M.
S. degree in Electrical Engineering, Computer Engineering or Computer Science with min. 4 years of experience in digital design /li liStrong communication and presentation skills /li liProactive mindset, strong problem solving skills, ability to work autonomously /li liKnowledge of RTL design /li liKnowledge of Testbench development /li liKnowledge of System Verilog and VHDL, Verilog /li /ul h3Preferred Qualification /h3 ul liKnowledge of mixed signal concepts /li liExperience in data path development h3Preferred Qualification /h3 ul liExperience in SoC architectures incl. CPU (ARM), Memory and Peripheral Subsystems /li liExperience with Synthesis, Timing Closure /li liExperience with Power Analysis and Optimization /li liExperience in Formal Verification Methodology /li liExperience in advanced Functional Verification Mythologies, i. e. UVM, Coverage modeling /li lixperience with scripting languages (TCL, Python, Perl, Shell-scripting) /li /ul pDesigns advanced digital and mixed-signal IPs and integrates on SoC for RF CMOS, high-speed data communication, data acquisition and low-power low-voltage applications. /p /li /ul