Senior Design Lead

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h3Career Opportunities: Senior Design Lead ) /h3pRequisition ID -Postedb11/09/2026 /b /ppDigital Validation: 8 to 10 years’ experience in FPGA design and validation /ph3Profile /h3ulliExperience in FPGA flow to take the design, adapt it and generate FPGA bit files. Masters the full FPGA flow from RTL to electrical validation /liliUnderstands and develops timing constraints specific to FPGA and analyses timing reports for the given design in consultation with design team. /liliProven experience in digital design concepts and code development in VHDL/Verilog/system Verilog. /liliExperience in adapting ASIC RTL code and replace blocks required to be able to fit it in an FPGA /liliGood understanding of timing issues in FPGA flow and how to address them, including clock domain crossings, clock generation, combinatorial loops. /liliProven experience with synplify synthesis tool, Vivado place and route tool, Xilinx FPGAs /liliExperience in writing C based tests for the FPGA testing. /liliExperience in Python based code development. /liliExperience in debug tools associated with FPGA debug. /liliStrong experience in electronics fundamentals and debug. /liliAbility to perform Device debug / Board debug and identify root cause, within an electrical validation environment. /liliNeed to be thorough at bench level validation Oscilloscope and digital analyzers. /liliFamiliar with revision control tools (SVN, run compute jobs) /li /ulh3Key Responsibilities /h3pDigital Validation: 8 to 10 years’ experience in FPGA design and validation /ph3Profile /h3ulliExperience in FPGA flow to take the design, adapt it and generate FPGA bit files. Masters the full FPGA flow from RTL to electrical validation /liliUnderstands and develops timing constraints specific to FPGA and analyses timing reports for the given design in consultation with design team. /liliProven experience in digital design concepts and code development in VHDL/Verilog/system Verilog. /liliExperience in adapting ASIC RTL code and replace blocks required to be able to fit it in an FPGA /liliGood understanding of timing issues in FPGA flow and how to address them, including clock domain crossings, clock generation, combinatorial loops. /liliProven experience with synplify synthesis tool, Vivado place and route tool, Xilinx FPGAs /liliExperience in writing C based tests for the FPGA testing. /liliExperience in Python based code development. /liliExperience in debug tools associated with FPGA debug. /liliStrong experience in electronics fundamentals and debug. /liliAbility to perform Device debug / Board debug and identify root cause, within an electrical validation environment. /liliNeed to be thorough at bench level validation Oscilloscope and digital analyzers. /liliFamiliar with revision control tools (SVN, run compute jobs) /li /ul

Senior Design Lead

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Senior Design Lead

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