FPGA Validation Design Engineer – Contract
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I am currently hiring for an FPGA Validation Design Engineer for an initial 3-month contract in Leuven, Belgium, offering hybrid working.
If you have relevant FPGA and semiconductor verification experience.
FPGA Validation Design Engineer – Contract
Location: Leuven, Belgium
Duration: Initial 3 months
Start Date: ASAP
Working Arrangement: Hybrid (3 days onsite, 2 days remote)
I'm currently recruiting an experienced FPGA Validation Design Engineer to join an exciting semiconductor project in Leuven.
Key Requirements:
- 5+ years of relevant semiconductor experience.
- ASIC RTL modification and FPGA integration.
- FPGA synthesis, place-and-route and timing closure.
- FPGA validation and board-level debugging.
- Experience with SystemVerilog, UVM and CPU/device verification.
- Fluent English.
This is a hands-on opportunity to work across FPGA implementation, validation and design verification, with some flexibility in working arrangements after induction.