FPGA Validation Design Engineer
Il y a 4 jours
VlaamsBrabant, Vlaams-Brabant, Belgique
Qplox engineering
Temps plein
50 000 € - 84 000 € Contrat
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Key Responsibilities
- Adapt and modify ASIC RTL for FPGA integration.
- Set up and execute FPGA development and verification flows.
- Perform FPGA database verification, synthesis, and place-and-route.
- Analyse timing reports, update constraints, and achieve timing closure.
- Debug FPGA bitstreams on hardware boards.
- Perform device- and CPU-level design verification.
Required Skills
- 5+ years of relevant semiconductor, FPGA, or design verification experience.
- Strong knowledge of SystemVerilog and UVM.
- Experience in device-level and CPU verification.
- Hands-on experience with RTL, FPGA implementation, timing analysis, and hardware debugging.
Start Date: ASAP
Project Duration: 3 months
Working Arrangement: Hybrid – 3 days onsite, 2 days remote (flexibility possible after induction)