Hybrid FPGA Validation Engineer

Il y a 4 jours

VlaamsBrabant, Vlaams-Brabant, Belgique Qplox engineering Temps plein 50 000 € - 84 000 €/an

Qplox engineering is seeking an FPGA/ASIC verification engineer to adapt RTL for FPGA integration and manage full verification flows. You will run FPGA development, perform synthesis, place-and-route, and analyze timing to achieve closure. The role requires hands-on debugging on hardware and experience with device and CPU verification.

The position is hybrid in Belgium (Vlaams-Brabant) with onsite and remote days, starting ASAP for a 3-month project.