Design Verification Engineer
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Duration: 3 months - Potential Extensions
Rates: Negotiable
Can your SystemVerilog skills turn ASIC RTL into silicon-ready FPGA prototypes in just three months?
An exciting 3-month contract is open for an experienced FPGA Validation Design Engineer to join a semiconductor design team on an immediate start. You’ll take ASIC RTL and bring it to life on FPGA, owning the flow end to end, from integration and synthesis through to timing closure and board-level debug, with a strong emphasis on design verification.
Responsibilities
- Modify ASIC RTL for integration into FPGA
- Set up and run the FPGA flow, including FPGA database verification
- Perform synthesis and place and route
- Drive timing closure, updating constraints to meet timing targets
- Debug bitmaps on FPGA boards
- Review product requirements and logic diagrams to support device definition
- Conduct experimental tests, evaluate results and document specifications
Skills required
- 5+ years’ relevant experience in FPGA / semiconductor design verification
- Strong verification background across complete devices and CPUs
- Hands-on SystemVerilog and UVM expertise
- Proven experience with synthesis, place and route and timing closure
- Comfortable with lab-based FPGA board debug
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