Principal Physical Design Engineer – SoC
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Nalys is seeking a Principal Physical Design Engineer to lead advanced SoC/IP physical design from RTL to GDSII, including floorplanning, power integrity, P&R, CTS, and STA. You will drive low-power strategies and standardize flows.
You will mentor engineers, optimize design methodologies, and evaluate next‑gen EDA tools to boost efficiency and quality in a fast-paced semiconductor environment. Jointly with architecture and verification teams, you will solve complex technical challenges.