Principal ASIC Physical Design Lead
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Nalys Group is seeking a Principal Physical Design Engineer for a major semiconductor client in Belgium. You will own the physical implementation from RTL to GDSII, focusing on floor planning, placing and routing, clock tree synthesis, and STA, while driving low-power strategies and automation improvements.
You will mentor engineers, lead design methodologies, and collaborate with cross-functional teams to ensure high-quality outcomes for next-generation SoC and IP blocks.