Physical ASIC Design Implementation Engineer

Il y a 20 heures

Leuven, Belgique imec Temps plein

Physical ASIC Design Implementation Engineer (temporary assignment)

Physical Implementation engineer for full backend (P&R) projects from netlist-in to GDSII-out flow, for toplevel chips aswell as blocklevel blocks in technologies ranging from N2 to 180nm. This with the full understanding of the complete Cadence Innovus Place&Route flow.

The assignment

  • Direct contact with our customers for future projects. 
  • Full understanding of the complete Cadence Innovus Place&Route flow. 
  • Take the lead for partitioning and split the top level SDC file into timing budget requirements/constraints of the sub-blocks. 
  • Work directly with the Physical Design implementation team during the entire chip design cycle to drive signoff closure for tape-out. 
  • Technical voice to the customer to discuss his specifications

Required knowledge and skills

  • Experience in setting-up the flow for the specific library set and foundry node used 
  • Experience in setting-up low power design (UPF) and debug sdc file 
  • Knowledge in Floorplanning & power grid design for toplevel aswell as blocks 
- Place, CTS & Routing 
- Solve setup & hold violations 
- Sign-off extraction (SPEF/QUANTUS) , timing (TEMPUS), Power analysis (VOLTUS) 
- Physical verification (DRC, ERC, LVS, ANT), Logic equivalent check

What we offer

We offer you an exciting temporary assignment in which you will be part of a community that makes the impossible possible. Together, we shape the technology that will define the society of tomorrow.
  • Duration of the assignment, 1 year, with extension if applicable
  • Desired start date: 01/05/2026
  • Work regime: full time

Location

We provide the flexibility to work both from our office premises and remotely from home. This to maintain a healthy work-life balance while being an integral part of our team. An onsite presence of 3 days a week is required. It's not possible to work 100% remote.