Senior CPU Subsystem RTL

Il y a 5 heures

Flemish Brabant, Flanders, Belgique Imec Temps plein
pImec in Leuven, Belgium, is seeking a Digital Designer to own RTL design of CPU-subsystem blocks and drive verification from unit tests to subsystem integration. The role focuses on SystemVerilog RTL, RISC-V cores, and integration with caches and interconnects. /ppYou will collaborate with multidisciplinary teams across the platform, prototypes and physical-aware design groups, and contribute to tape-out readiness while addressing PPA and timing implications. /p