Senior DFT Engineer: Lead Testability for Next-Gen Chips

Il y a 17 heures

Leuven, Flanders, Belgique Imec Temps plein
IMEC in Leuven, Belgium seeks a Senior DFT Engineer to drive design-for-test for SOCs in cutting-edge semiconductor projects. You will architect DFT solutions, coordinate requirements with teams and customers, and implement innovative techniques across complex IP and large-scale designs. Join a world-class R&D environment, collaborating with physical design and test engineering to validate silicon and optimize fault coverage.