h3We Are /h3 pSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their RD capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. /p h3You Are /h3 pYou have spent years in the trenches of custom layout, working on designs where a 10-micron mistake costs months and where matching, symmetry, and parasitic control are not nice-to-haves but the entire point. You know that a great floorplan is not about fitting everything in, it is about making the right tradeoffs between area, routing congestion, and signal integrity before anyone writes a single polygon. You have debugged EMIR violations at 3am and walked out knowing exactly which power stripe needed to move and why. /p pYou do not just execute layouts, you think about them. When someone hands you a schematic, you are already mentally placing critical pairs, planning guard rings, and asking about the ESD strategy. You have worked in 7nm or below, and you understand that FinFET and GAA are not just smaller nodes, they are different games with different rules. You mentor without micromanaging, you lead without needing the title, and you care about the quality of what ships, not just what closes timing. /p pAt Synopsys, you will work on DDR and HBM PHY IP that powers the memory subsystems in everything from data centers to AI accelerators. The work is hard, the standards are high, and the team expects you to bring both hands and brain. /p h3What You'll Be Doing /h3 ul liLead layout development for next-generation DDR and HBM PHY IP across 7nm, 5nm, and below in FinFET and GAA process technologies /li liOwn floorplanning, layout execution, and design reviews for critical analog and mixed-signal blocks within memory PHY subsystems /li liDrive layout quality through PERC, EMIR, DFM checks, LEF generation, and release readiness, ensuring designs meet foundry and customer specifications /li liCollaborate with circuit design, verification, and product engineering teams to resolve layout-related issues, optimize for area and performance, and meet project schedules /li liMentor junior layout engineers on matching techniques, ESD and latch-up strategies, IO frame requirements, and deep submicron layout best practices /li liEstimate effort, plan schedules, and execute layout deliverables in cross-functional project settings with accountability for timelines and quality /li liSupport customer-specific PHY requirements including bond-pad layout, pitch constraints, and custom IO configurations /li /ul h3The Impact You Will Have /h3 ul liEnable Synopsys customers to integrate high-performance, low-power memory subsystems into SoCs powering AI, 5G, automotive, and cloud applications /li liAccelerate time-to-market for next-generation DDR and HBM IP by delivering layout that works the first time and scales across process nodes /li liRaise the technical bar for the layout team through hands-on mentorship, design reviews, and shared best practices that improve quality and efficiency /li liReduce design respins and foundry-related issues by catching deep submicron effects, parasitic mismatches, and DFM violations early in the layout cycle /li liStrengthen cross-functional collaboration between layout, circuit design, and product teams, ensuring alignment on requirements, schedules, and tradeoffs /li liBuild reusable layout methodologies and IP blocks that scale across future memory PHY products and process technologies /li liContribute to Synopsys Silicon IP's reputation for delivering world-class, production-proven memory interface solutions /li /ul h3What You'll Need /h3 ul liBachelor's or Master's degree in Electronics Engineering, VLSI Design, or related field /li li5+ years of hands-on custom layout experience, with demonstrated leadership on complex analog or mixed-signal IP projects /li liDeep expertise in layout for 7nm and below process nodes, including FinFET and GAA technologies, with strong understanding of deep submicron effects /li liProficiency in layout matching techniques, ESD and latch-up design, PERC, EMIR analysis, DFM checks, and LEF generation /li liExperience with PHY-level IP development, including bond-pad layout, IO frame design, and customer pitch requirements /li liProven ability to lead projects, estimate effort, plan schedules, and deliver high-quality layout on time in cross-functional settings /li liExperience with DDR, HBM, or high-speed memory interface IP is a strong plus /li /ul h3Who You Are /h3 ul liYou can look at a floorplan and immediately spot the congestion bottleneck or the block that is going to cause EMIR headaches three months from now /li liYou explain layout tradeoffs to circuit designers and product managers in terms they unde
