Runtime-Integrated Simulation of Accelerator Memory Behaviour for Distributed LLM Deployment
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Runtime-Integrated Simulation of Accelerator Memory Behaviour for Distributed LLM Deployment
Where hardware meets software: integrate hardware simulation where it matters.
Developing hardware for AI is both costly and technicallydemanding. The software stack evolves rapidly and is often optimized aroundGPUs. These realities raise a fundamental challenge: how can one validatehardware that does not yet exist for emerging AI workloads? Fortunately, mostAI applications are built on a relatively small set of frameworks, notablyPyTorch and JAX, which provide natural integration pathways for newaccelerators. Hooking into the integration layers from software frameworks tohardware offers a practical interface for accelerator simulators to assess bothfunctional correctness and performance characteristics.
Taking inspiration from PyTorch's example acceleratorintegration (OpenReg), this internship effort focuses on simulating acceleratormemory behaviour during distributed LLM deployment. The goal is to enableearly-stage evaluation of memory bottlenecks, communication patterns, andexecution efficiency before hardware is physically available, thereby reducingdesign risk and accelerating the development cycle for novel AI accelerators.
Objectives
- develop a simulator for faithfully modelling acceleratormemory behaviour in distributed LLM execution;
- integrate the model with existing PyTorchexecution paths to capture realistic memory access patterns;
- analyze memory usage, identify potential memorybottlenecks under distributed deployment scenarios;
- disseminate the findings by publishing inappropriate conference or journal.
Desirable skills
- Familiarity with Python and C++; experience with PyTorch is a plus
- Interest in computer architecture; knowledge of architectural simulators suchas gem5 and onnxim is a plus
- Basic familiarity with LLM models and distribution strategies
Type of internship: Master internship, PhD internship
Duration: 6 months
Required educational background: Computer Science, Electrotechnics/Electrical Engineering
University promotor: Debjoti Bhattacharjee (KULeuven)
Supervising scientist(s): Nathan Laubeuf
The reference code for this position is 2026-INT-327. Mention this reference code in your application.
- Imec allowance will be provided.
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